`ifndef FIFO_REFERMODULE__SV
`define FIFO_REFERMODULE__SV

`include "fifo_transcation.sv"

class fifo_refermodule extends uvm_component;
	
	`uvm_component_utils(fifo_refermodule);
	//fifo_transcation tr_in  ;
	//fifo_transcation tr_out ;
	
	uvm_blocking_get_port#(fifo_transcation) bg_port;
	//uvm_analysis_imp#(fifo_transcation,fifo_refermodule) a_imp;
	function new(string name = "fifo_refermodule",uvm_component parent = null);
		super.new(name,parent);
	endfunction

	function void build_phase(uvm_phase phase);
		super.build_phase(phase);
		`uvm_info("fifo_refermodule","build_phase is called",UVM_LOW)
		bg_port = new("bg_port",this);
		//a_imp = new("a_imp",this);
	endfunction
	
	/* task write(fifo_transcation tr);
		//main_phase(uvm_phase phase);
		$display("port trans damc is %d",tr.dmac);
	endtask */
	
	
	extern virtual task main_phase(uvm_phase phase);
endclass
	
task fifo_refermodule::main_phase(uvm_phase phase);
	fifo_transcation tr_in  ;
	fifo_transcation tr_out ;
	
	`uvm_info("fifo_refermodule","main_phase is called",UVM_LOW)
	super.main_phase(phase);
	 
	while(1) begin
	`uvm_info("fifo_refermodule",$sformatf("time is %d",$time),UVM_LOW)
	bg_port.get(tr_in);
	`uvm_info("fifo_refermodule",$sformatf("after get pkt time is %d",$time),UVM_LOW)
	tr_out = new("tr_out");
	tr_out.copy(tr_in);
	`uvm_info("fifo_refermodule","get one dmac",UVM_LOW)
	tr_out.my_print();
	end 
	
endtask

`endif
